1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, an apparatus for manufacturing a semiconductor device, a program for manufacturing a semiconductor device, and a program for generating mask data. More particularly, the present invention relates to a method for manufacturing a semiconductor device, an apparatus for manufacturing a semiconductor device, a program for manufacturing a semiconductor device, and a program for generating mask data that predict a portion that will remain as a step difference in a case where a planarizing film on a pattern is to be planarized and reflect the existence of the portion in the correction of a layout and in manufacturing conditions.
2. Description of the Related Art
As one of technologies for dealing with higher integration of semiconductor integrated circuits, a planarization process has been performed when semiconductor integrated circuits are to be manufactured. One example of the planarization processing technologies is a chemical mechanical polishing method (hereinafter sometimes referred to as a “CMP method”).
FIG. 18 is a conceptual view of a polishing device for use in a CMP method. This polishing device includes a polishing plate, a substrate holding base, and an abrasive slurry supply system. The polishing plate is movably supported by the rotational axle of the polishing plate, which rotates, and the surface thereof is provided with a polishing pad.
The substrate holding base is arranged above the polishing plate and is movably supported by the rotational axle of the substrate holding base. For example, in a case where a substrate is to be polished, the substrate is placed on the substrate holding base. The rotational axle of the substrate holding base is mounted in a polishing pressure adjustment mechanism (not shown) that presses the substrate holding base in the direction of the polishing pad.
Then, the polishing plate is rotated while an abrasive slurry containing an abrasive agent is supplied from the abrasive slurry supply system to the polishing pad. At the same time, while the substrate placed on the substrate holding base is being rotated, the polishing pressure of the substrate with respect to the polishing pad is adjusted by the polishing pressure adjustment mechanism. In the manner described above, it is possible to polish the surface of the substrate.
Here, when, after a thin film has been formed on a circuit pattern, the formed thin film is to be planarized by a CMP method, prediction in advance of the thickness of the thin film after planarization is very important for the purpose of solving problems at an early stage and reducing the manufacturing cost in the manufacture of semiconductor devices. Furthermore, in analysis of characteristics of the semiconductor device, that is, from the viewpoint of ensuring timing convergence in an integrated circuit, in particular, RC extraction (parasitic resistance, parasitic capacitance extraction), information on the cross-sectional structure of the semiconductor device is used. Therefore, by predicting in advance the value of the film thickness of a thin film that is to be formed on a circuit pattern and planarized, it is possible to shorten the time taken to achieve timing convergence and to feed back and use the information in the layout of components, such as a dummy fill.
To date, as techniques for predicting film formation and polishing processes, simulation technologies have been proposed (see, for example, Japanese Patent No. 3580036, Japanese Patent No. 3743120, Japanese Unexamined Patent Application Publication No. 2007-103634, Japanese Unexamined Patent Application Publication No. 2008-4683, and Japanese Unexamined Patent Application Publication No. 10-144635).
In Japanese Patent No. 3580036, a simulation method is disclosed for predicting the shape of a step difference that will remain after polishing is performed for a predetermined time period. That is, in a case where CMP is performed using a polishing cloth, a pressure distribution due to stress modification that is given to the polishing cloth by a step-difference shape is calculated by the finite element method, and this distribution is converted into a polishing rate so as to predict a processed shape after a unit time period.
In Japanese Patent No. 3743120, a technique is disclosed for predicting the amount of film that will remain after polishing on the basis of an area ratio. Japanese Unexamined Patent Application Publication No. 2007-103634 is directed to a technology for considering the film formation state before polishing at the time of calculations after polishing by changing the area ratio; in particular, a technology that considers the amount of conversion of the pattern width of the film formation by O-TEOS and HDP has been proposed. Furthermore, a polishing pressure is calculated on the basis of the area ratio of the pattern after conversion, and is converted into a polishing rate so as to calculate the amount of polishing.
In Japanese Unexamined Patent Application Publication No. 2008-4683, a technique is disclosed in which the film thickness after plating is calculated by using a model created by a calibration method so as to obtain the film thickness after polishing.
Additionally, in Japanese Unexamined Patent Application Publication No. 10-144635, a technology is disclosed in which the relationship between step-difference densities and film-thickness step differences is determined in advance in a test element group (TEG), the area density in the actual layout is calculated, and a dummy portion is generated in portions in which a predetermined step-difference threshold value is exceeded.